1. Field of the Invention
This invention relates to an information processor with a delayed interrupt device having a function of delaying the processing of an interrupt request until a predetermined condition is satisfied, if the interrupt request such as a delayed interrupt request to be executed has occurred during the execution of another process, and processing the interrupt request after the completion of another process.
2. Description of the Prior Art
Among processes to be executed in an information processor, there is a process that must be completed with no interruption, once it is started. This kind of process is called an indivisible process and hereinafter referred to as the process P. The process P is, for example, a process that must be completed within a defined time, or a read/write process or an accessing process that handles a certain object R such as a specific region in a memory or a specific I/O device.
There are three types of the interrupt processes, an external interrupt request, a software interrupt request, and a delayed interrupt request.
During the execution of the process P, an external interrupt request of executing another process I may occur. Since it is impossible to execute the process I at once, the request of process I is stored, and after the completion of the process P, the process I is executed. Namely, the interrupt process I is delayed.
To delay the process I, the information processor usually has a delayed interrupt function.
FIG. 1 is a block diagram roughly explaining the delayed interrupt function of the information processor.
In the figure, the information processor 21 has an instruction execution unit 25 for reading programs from a memory 23 and successively processing the read programs. Among processes to be executed by the instruction execution unit 25, there is time indivisible process P.
If the instruction execution unit 25 detects, during the execution of the process P, certain condition to issue a request of executing another process I, the instruction execution unit 25 sends a delayed interrupt request 201 to a delayed interrupt memory circuit 27, instead of executing the process I at once. The delayed interrupt memory circuit 27 stores the request.
A delayed interrupt signal generator 29 generates a delayed interrupt signal 203 according to the data stored in the delayed interrupt memory circuit 27. The signal 203 is transferred to time instruction execution unit 25 through a delayed interrupt inhibition circuit 31.
The delayed interrupt inhibition circuit 31 does not issue an interrupt signal 205 if a status register 33 of the instruction execution unit 25 contains a value D indicating that time process P is being executed, and if the same contains a value E indicating that the process P is not being executed, issues the interrupt signal 205 corresponding to time delayed interrupt signal 203 to the instruction execution unit 25.
The instruction execution unit 25 keeps the value D in the status register 33, while executing the process P. If the status register 33 is holding the value D, therefore, the delayed interrupt inhibition circuit 31 does not provide the interrupt signal 205. After the completion of the process P, the instruction execution unit 25 changes the contents of the status register 33 to the value E indicating that the process P is not being executed. The delayed interrupt inhibition circuit 31 then generates the interrupt signal 205, and upon receiving the interrupt signal 205, the instruction execution unit 25 suspends a presently executing process and starts executing the process I.
A conventional information processor having the delayed interrupt function will be explained with reference to a block diagram of FIG. 2.
In the figure, the information processor, represented with numeral 21, has a 4-bit register 35 called a delayed interrupt (DI), which stores any one of numerals H'0 to H'f. Here, H' means that the following numeral is a hexadecimal numeral.
An instruction execution unit 25 of the information processor 21 has a 4-bit register 37 called IMASK, which stores any one of numerals H'0 to H'f. When the numeral stored in the DI 35 is smaller than the numeral stored in the IMASK 37, a comparator 39 sends the contents of the DI 35 as an interrupt signal 205 to the instruction execution unit 25, and according to the signal 205, the instruction execution unit 25 executes an interrupt process.
Usually, the IMASK 27 and DI 35 store each H'f. A process I is registered in the instruction execution unit 25 as an interrupt process corresponding to an interrupt signal H'e. Before executing the process P, the instruction execution unit 25 sets the IMASK 37 to, for example, H'e that is smaller than H'f. The content of the IMASK 37 is reset again to H'f after the completion of the process P.
If the process I to be executed occurs during the execution of the process P, the instruction execution unit 25 does not execute the process I at once but writes H'e in the DI 35 with a delayed interrupt request 201. At this time, the numeral stored in the DI 35 is not smaller than the numeral stored in the IMASK 37, so that the comparator 39 does not issue the interrupt signal 205.
After completing the process P, the instruction execution unit 25 sets H'f in the IMASK 37. The numeral stored in the DI 35 then becomes smaller than the numeral stored in the IMASK 37, and therefore, the comparator 39 sends the contents H'e of the DI 35 as the interrupt signal 205 to the instruction execution unit 25. Upon receiving the signal 205, the instruction execution unit 25 suspends a presently executing process and executes the interrupt process I corresponding to the interrupt signal H'e.
This conventional information processor 21 does not execute the interrupt process of the process I during the execution of the process P but stores the request of executing the process I as the delayed interrupt request 201 to delay the execution of the process I until the process P is completed.
The information processor 21, however, can store only one delayed interrupt request 201. In the above example, for example, if another interrupt request corresponding to a numeral H'd is to be stored in the DI 35 while the DI 35 is holding the numeral H'e as the delayed interrupt request 201, the previously stored numeral H'e will be abandoned. As a result, the execution request of the process I will be lost. In this way, this information processor 21 cannot store a plurality of delayed interrupt requests.
Another conventional information processor will be explained with reference to FIG. 3.
This information processor, represented with numeral 21, has a register 41, which comprises 15 bits numbered from H'1 to H'f.
An instruction execution unit 25 of the information processor 21 has a 4-bit register 37 (referred to as the IMASK 37), which stores any one of numerals H'0 to H'f.
A priority encoder 43 provides a smallest one of bit numbers of the register 41 where H'1 is stored.
A comparator 39 compares the bit number provided by the priority encoder 43 with a numeral stored in the IMASK 37, and if the former is larger than the latter, provides the former bit number as an interrupt signal 205 to the instruction execution unit 25. Upon receiving the interrupt signal 205, the instruction execution unit 25 executes the interrupt process.
Usually, the IMASK 37 stores H'0, and each bit of the register 41 stores 0. The process I is registered in the instruction execution unit 25 as all interrupt process corresponding to a signal H'8. Before executing the process P, the instruction execution unit 25 sets the IMASK 37 to a value larger than H'8, for example, H'f.
If a request of the process I to be executed occurs during the execution of the process P, the instruction execution unit 25 does not execute the process I at once but writes H'1 in the "H'8"th bit of the register 41. This writing process is carried out with a delayed interrupt request 201. At this time, an output 203 of a priority encoder 43 is H'8, which is not larger than the numeral stored in the IMASK 37, so that the comparator 39 does not generate the interrupt signal 205.
After the completion of the process P, the instruction execution unit 25 sets H'0 in the IMASK 37. At this time, the output of the priority encoder 43 becomes larger than the contents of the IMASK 37, and therefore, the comparator 39 supplies the output H'8 of the priority encoder 43 as the interrupt signal 205 to the instruction execution unit 25. Upon receiving the signal 205, the instruction execution unit 25 executes the interrupt process I corresponding to the interrupt signal H'8.
The information processor 21 stores up to 16 execution requests. In the above example, the "H'8"th bit of the register 41 used for the execution request of the process I. To further store an execution request of another process J, the process J may be registered in advance in the information processor 21 as an interrupt process corresponding to, for example, an interrupt signal H'9. When the delayed interrupt request 201 is issued for the process J, a numeral H'1 will be written in the "H'8"th bit of the register 41. If the numeral stored in the IMASK 37 becomes smaller than H'8, an interrupt request corresponding to the "H'8"th bit of the register 41 is generated to execute the process I, and when the numeral stored in the IMASK 37 becomes smaller than H'9, an interrupt request corresponding to the "H'9"th bit of the register 41 is generated to execute the process J.
According to this information processor 21, the delayed interrupt request 201 is stored in the register 41, then processed in an ascending order of bit numbers, irrespective of the order of generation of each request. Further, each bit of the register 41 stores only one corresponding delayed interrupt request 201. For example, if two requests occur for the process I and if a value H'1 is written two times in the "H'8"th bit of the register 41, this makes no sense.
In this way, the conventional information processor of FIG. 2 stores only a single delayed interrupt request to execute the same after a certain delay time, and cannot store a plurality of delayed interrupt requests. On the other hand, the conventional information processor of FIG. 3 stores a plurality of delayed interrupt requests but cannot store the order of occurrence of the delayed interrupt requests and cannot repeatedly store the same delayed interrupt request.